1. Field of the Invention
The present invention relates to a thin-film capacitor device, to be assembled into a semiconductor module, and to a method for fabricating the same. More particularly, the invention relates to a thin-film capacitor device which is a thin-film capacitor adapted to be mounted on a printed wiring board together with an LSI device, wherein provisions are made to suppress the generation of parasitic inductance and to reduce the size of the capacitor device by reducing the core substrate thickness, and the invention also relates to a mounting module and a fabrication method for the same.
2. Description of the Related Art
In recent years, in the field of digital LSI semiconductor devices used in electronic apparatuses, work has been proceeding toward reducing supply voltages for faster operating speeds and lower power consumption. In such an LSI, as the supply voltage for operating the LSI can become unstable due to rapid variations in impedance, etc., a bypass capacitor is placed between the voltage supply line of the LSI and the ground line to stabilize the supply voltage. Furthermore, stable operation in higher frequency (GHz) regions is demanded of high-speed digital LSIs and, to meet this demand, provisions are made to reduce high-frequency noise and prevent the LSIs from malfunctioning due to high-frequency noise.
Conventionally, a chip capacitor is used as the bypass capacitor, and this chip capacitor is mounted in close proximity to an LSI chip on a circuit board which is a motherboard. However, as wiring leads must be routed between the chip capacitor and the LSI chip, a relatively large inductance exists between these leads. As a result, even if the chip capacitor is provided, its effectiveness in suppressing variations in supply voltage and reducing high-frequency noise is substantially reduced in the case of a high-speed LSI.
The bypass capacitor is provided for reducing the equivalent series resistance and equivalent series inductance of substrate circuitry, but the increase in inductance due to the routing between the bypass capacitor and the LSI results in degrading the high-frequency characteristics of the bypass capacitor. To address this difficulty, a capacitor device designed so as to place the bypass capacitor directly below the LSI, thereby minimizing the wiring distance between the LSI and the bypass capacitor and thus reducing the inductance, is disclosed, for example, in Japanese Unexamined Patent Publication No. 2002-8942.
For example, in the case of a capacitor device constructed so as to minimize the wiring distance between the LSI and the capacitor and reduce the inductance by building the capacitor into the motherboard formed from a ceramic circuit substrate, there arise problems such as the following: the baking temperature of a high dielectric material for forming a capacitor insulating film, in the case of the ceramic circuit substrate, is as high as 700° C.; the fabrication process involves difficulty in stacking ferroelectric layers; there are limitations in improving the fabrication yield of the ceramic circuit substrate with a built-in capacitor; and there are limitations in the miniaturization process for forming through-holes in the ceramic circuit substrate at a reduced wiring pitch.
According to the prior art bypass capacitor device having the earlier described construction, the above-enumerated problems can be addressed, and a bypass capacitor device capable of being used with a high-speed digital LSI can be produced. Thus, the prior art has been able to provide a capacitor device that can reduce the required mounted area on the circuit substrate and yet has large capacitance for use in high frequency regions.
In the above-proposed capacitor device, however, a substrate formed from elemental silicon or from a silicon-containing insulating film or sapphire or the like, and having a thickness of 300 μm, is used as the core substrate that forms the base of the capacitor, and through-holes, into which conductive material is filled, are opened in the substrate in order to connect between the plurality of upper electrode pads on the LSI side and the plurality of lower electrode pads on the circuit substrate side. After the through-holes have been opened in the core substrate, the thickness of the core substrate determines the thickness of the capacitor device.
The operation of recent digital LSIs demands higher speed characteristics and, to meet this demand, the capacitor device must be further reduced in size and the characteristics of the package must be improved by reducing the wiring length between the capacitor device and the circuit substrate, as well as between the LSI and the capacitor device, thereby reducing parasitic inductance. There is therefore a need to further reduce the thickness of the core substrate forming the capacitor device; in particular, it is desired to reduce the thickness to 50 μm or less. However, in the prior art capacitor device, as the capacitor fabrication sequence requires that the through-holes be opened first, there arises the problem that there is a limit to further reducing the thickness of the core substrate in the fabrication process.
Furthermore, in the bypass capacitor according to the prior art capacitor device, the capacitor insulating film is formed by sputtering a high dielectric material, but the capacitor must be formed in a low-temperature process in order to prevent the deformation, etc. of the core substrate, due to the heat, during the processing.
The present invention has been devised in view of the above problem, and an object of the invention is to provide a thin-film capacitor device that can easily provide large capacitance, permits the use of a miniaturization process, and can reduce the required mounting area on the circuit substrate; it is also an object of the invention to provide a mounting module and a fabrication method for the same.